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Volume : IX, Issue : II, March - 2019 Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes Dr. Rekha, - By : Laxmi Book Publication Abstract : In order to mitigate the threat posed by quantum computing to cryptographic security, this work presents a hardware accelerator to enable multiple Post-Quantum Cryptosystem (PQC) approaches. Even though PQCs are more secure, they also come with high computational requirements, which are problematic for lightweight devices in particular Keywords : Article : Cite This Article : Dr. Rekha, -(2019). Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes. Indian Streams Research Journal, Vol. IX, Issue. II, http://isrj.org/UploadedData/11099.pdf References : - 2. Katzenbeisser, S.; Polian, I.; Regazzoni, F.; Stöttinger, M. Security in Autonomous Systems. In Proceedings of the 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 27–31 May 2019; pp. 1–8. https://doi.org/10.1109/ETS.2019.8791552.
- 1. Carracedo, J.M.; Milliken, M.; Chouhan, P.K.; Scotney, B.; Lin, Z.; Sajjad, A.; Shackleton, M. Cryptography for Security in IoT. In Proceedings of the 2018 Fifth International Conference on Internet of Things: Systems, Management and Security, Valencia, Spain, 15–18 October 2018; pp. 23–30. https://doi.org/10.1109/IoTSMS.2018.8554634
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